1. Field of Invention
The present invention relates to semiconductor technique, and more particularly, to a method of adjusting a metal gate work function of an NMOS device, which can be used for fabricating a high performance complementary metal-oxide-semiconductor (CMOS) device of 45 nanometers and beyond.
2. Description of Prior Art
As a feature size of a CMOS device reaches 45 nm and beyond, it is well known in the art that a conventional SiO2/poly-Si (polycrystalline silicon) gate stack structure needs to be replaced with a high K (dielectric constant)/metal gate stack structure, so as to significantly reduce tunneling current and resistance of the gate, to eliminate a depletion effect of the polycrystalline silicon gate, to improve reliability of the device, and to alleviate a Fermi level pinning effect. However, there are many challenges in integration of the metal gate with the high K dielectric, such as challenges regarding thermal stability and interfacial states. Specifically, the Fermi level pinning effect results in a big challenge in a nano CMOS device which should have an appropriately low threshold voltage.